Most conventional wire routing design programs produce a wire layout connecting certain predefined locations or points (herein referred to as logic service terminals or LSTs), which typically reside in alignment with a predetermined fixed grid pattern. Traditionally, these on-grid logic service terminals have been aligned over the particular input structure (such as a transistor gate) or output structure (e.g., an output diffusion) of the function block to be connected within the circuit.
By way of example, FIG. 1 depicts a fixed wiring grid layout 12 wherein a first global metallization layer (M1) is arranged in a horizontal direction and a second global metallization layer (M2) is arranged substantially orthogonal thereto such that a grid of intersecting points 10 is defined. Most wire routing programs assume that the connect locations (LSTs) are on-grid, i.e., aligned with points 10. (Traditionally, wiring comprising a third global metallization level (M3) (not shown) is also used. This third level would substantially align with metallization level (M1).) In one implementation, the first level metal (M1) is shared between function block wiring and horizontal global wiring, the second level metal (M2) is used for vertical global wiring and the third level metal (M3) (not shown) is used for further horizontal global wiring.
Typically, each function block to be wired in an integrated circuit typically contains at least one, and normally more than one, logic service terminal (LST). These LSTs identify a particular location on the associated function block where the wiring layout can connect to either an input structure or output structure, such as a transistor gate or a diffusion. Typically, each function block has multiple transistor gates to be wired within the circuit, either to structures within the function block or globally. Where multiple transistor gates per function block exist, the pitch of the gates and the pitch of the second level metal (M2) have traditionally been maintained the same in order that the gate structures align with the LSTs of the global wiring grid for ready connection thereto. Unfortunately, for a given technology, optimum wiring pitch for the second metal level (M2) (which again operates in part to define the wiring grid) is often different than the optimum pitch of a function block's transistor gates. For example, a preferred second level metal (M2) pitch may be 2.4 microns, while an optimum gate pitch may be 2.6 microns. There are several known approaches to addressing this problem, but each has its own disadvantages.
One approach is to simply increase the second level metal (M2) pitch to that of the transistor gate pitch, e.g., to 2.6 microns. However, this results in fewer available global wires on the most critical wiring level (i.e., the vertical global wiring level) and therefore a reduced chip density. Another possible technique is to reduce the global wiring grid to a value that is a factor of both the transistor gate and the global wiring pitches. For example, the gate pitch could be changed to 3.2 microns and the grid pitch to 0.8 microns, or the gates could be left at 2.6 microns pitch and the grid pitch changed to 0.2 microns. However, either change produces a much greater data volume for the wiring design program, and therefore reduced performance. In addition, the first suggested change also results in a reduced chip density.
A further approach is to leave the second metal level (M2) and gate pitches at 2.4 microns and 2.6 microns, respectively, and to place the logic service terminals in alignment with grid points by appropriately configuring the gates. FIG. 2 is a simplified depiction of a function block 20 constructed using this approach. Block 20 includes three input gate structures 22a, 22b and 22c, which reside over two separate diffusions 23. Gate 22a has three logic service terminals 24a associated therewith, while gates 22b and 22c each have two logic service terminals 24b and 24c, respectively. Few LSTs per gate are possible since according to this approach the LSTs can only be positioned in alignment with the wiring grid (not shown). This complicates the wiring layout process and results in a lower utilization of silicon area.
In view of the identified problems associated with the known on-grid approaches, an off-grid wiring layout technique is considered desirable. One commercially available wiring tool provides for global wiring layout wherein the logic service terminals are located off-grid relative to the global wiring. This product is marketed by Cadence Design Systems, Inc. of San Jose, Calif. under the Trademark CELL3. Unfortunately extensive run times are required to operate the program when the LSTs are off-grid, causing some chip physical designers not to take advantage of this aspect of the CELL3 wiring tool.
Therefore, a more efficient approach to producing a wiring layout wherein desired contacts are off-grid is needed, and particularly one which allows minimum pitch for both gates and wires, a plurality of logic service terminals along an entire gate and much greater flexibility for the circuit designer. The present invention provides such a wiring layout design technique.